Renesas RL78 Series User Manual page 440

RL78/G1D
Figure 13-39. Flowchart of Master Reception (in Continuous Reception Mode)
Write 1 to MDmn0 bit
Remark <1> to <8> in the figure correspond to <1> to <8> in Figure 13-38 Timing Chart of Master
Reception (in Continuous Reception Mode).
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Starting CSI communication
SAU default setting
<1>
Setting receive data
Enables interrupt
Writing dummy data to
<2>
SIOp (=SDRmn[7:0])
Wait for receive completes
<3> <6>
Buffer empty/transfer end interrupt
BFFmn = 1?
Yes
<4>
Reading receive data from
SIOp (=SDRmn[7:0])
<7>
Subtract -1 from number of
transmit data
= 0
Number of communication
data?
= 1
<5>
Clear MDmn0 bit to 0
RETI
No
Number of communication
data = 0?
Yes
Yes
Communication continued?
No
Disable interrupt (MASK)
<8>
Write 1 to STmn bit
End of communication
CHAPTER 13 SERIAL ARRAY UNIT
For the initial setting, refer to Figure 13-32.
buffer empty
(Select interrupt)
Setting storage area of the receive data, number of communication data
(Storage area, Reception data pointer, Number of communication data and
Communication end flag are optionally set on the internal RAM by the software)
Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set
interrupt enable (EI)
Writing to SIOp makes SCKp
signals out (communication starts)
When interrupt is generated, it moves to
interrupt processing routine
No
Read receive data, if any, then write them to storage
area, and update receive data pointer (also subtract -1
from number of transmit data)
≥ 2
<2>
Writing dummy data to
SIOp (=SDRmn[7:0])
When number of communication data
becomes 0, receive completes
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