Renesas RL78 Series User Manual page 822

RL78/G1D
Instruction
Mnemonic
Group
16-bit MOVW BC, !addr16
data
BC, ES:!addr16
transfer
DE, !addr16
DE, ES:!addr16
HL, !addr16
HL, ES:!addr16
BC, saddrp
DE, saddrp
HL, saddrp
XCHW AX, rp
ONEW AX
BC
CLRW AX
BC
8-bit ADD A, #byte
operation
saddr, #byte
A, r
r, A
A, !addr16
A, ES:!addr16
A, saddr
A, [HL]
A, ES:[HL]
A, [HL+byte]
A, ES:[HL+byte]
A, [HL+B]
A, ES:[HL+B]
A, [HL+C]
A, ES:[HL+C]
Notes 1. Number of CPU clocks (f
when no data is accessed.
2. Number of CPU clocks (f
accessed by an 8-bit instruction.
3. Except rp = AX
4. Except r = A
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction
from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Table 29-5. Operation List (6/17)
Operands Bytes
Note 1 Note 2
3
4
3
4
3
4
2
2
2
Note 3
1
1
1
1
1
2
3
Note 4
2
2
3
4
2
1
2
2
3
2
3
2
3
) when the internal RAM area, SFR area, or extended SFR area is accessed, or
CLK
) when the code flash memory is accessed, or when the data flash memory is
CLK
Clocks
1 4 BC ← (addr16)
2 5 BC ← (ES, addr16)
1 4 DE ← (addr16)
2 5 DE ← (ES, addr16)
1 4 HL ← (addr16)
2 5 HL ← (ES, addr16)
1 – BC ← (saddrp)
1 – DE ← (saddrp)
1 – HL ← (saddrp)
1 – AX ← rp
1 – AX ← 0001H
1 – BC ← 0001H
1 – AX ← 0000H
1 – BC ← 0000H
1 – A, CY ← A + byte
2 – (saddr), CY ← (saddr)+byte
1 – A, CY ← A + r
1 – r, CY ← r + A
1 4 A, CY ← A + (addr16)
2 5 A, CY ← A + (ES, addr16)
1 – A, CY ← A + (saddr)
1 4 A, CY ← A+ (HL)
2 5 A,CY ← A + (ES, HL)
1 4 A, CY ← A + (HL+byte)
2 5 A,CY ← A + ((ES, HL)+byte)
1 4 A, CY ← A + (HL+B)
2 5 A,CY ← A+((ES, HL)+B)
1 4 A, CY ← A + (HL+C)
2 5 A,CY ← A + ((ES, HL) + C)
CHAPTER 29 INSTRUCTION SET
Operation Flag
Z AC CY
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
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