Renesas RL78 Series User Manual page 184

RL78/G1D
Figure 7-2. Internal Block Diagram of Channels 0, 2, 4, 6 of Timer Array Unit 0
Input signal from the master channel
CK00
f
MCK
CK01
Edge
TI0n
detection
Channel n
Input signal to the slave channel
Notes 1. Channels = 2, 4, 6 only
2. n = 2, 4, 6 only
Remark n = 0, 2, 4, 6
Figure 7-3. Internal Block Diagram of Channel 1 and 3 of Timer Array Unit 0
CK00
CK01
f
MCK
CK02
CK03
Edge
TI0n
detection
Channel n
Remark n = 1, 3
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Note 1
Timer controller
f
TCLK
Slave/master
controller
Note2
CKS0n CCS0n MAS
TER0n
Input signal from the master channel
f Timer controller
TCLK
SPLIT
CKS1n CKS0n CCS0n
0n
Output
controller
Mode
selection
Interrupt
controller
Timer counter register 0n (TCR0n)
Timer data register 0n (TDR0n)
STS0n2 STS0n1 STS0n0 CIS0n1CIS0n0 MD0n3
Timer mode register 0n (TMR0n)
Output
controller
Mode
selection
Interrupt
controller
Timer counter register 0n (TCR0n)
Timer data register 0n (TDR0n)
8-bit timer
controller Interrupt
controller
Mode
selection
STS0n2 STS0n1STS0n0 CIS0n1CIS0n0 MD0n3
Timer mode register 0n (TMR0n)
CHAPTER 7 TIMER ARRAY UNIT
Output latch
(Pxx)
INTTM0n
(Timer interrupt)
Timer status
register 0n (TSR0n)
OVF
0n
Overflow
MD0n2 MD0n1 MD0n0
Output latch
(Pxx)
INTTM0n
(Timer interrupt)
Timer status
register 0n (TSR0n)
OVF
0n
Overflow
INTTM0nH
(Timer interrupt)
MD0n2 MD0n1 MD0n0
TO0n
PMxx
TO0n
PMxx
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