Renesas RL78 Series User Manual page 778

RL78/G1D
<R> Note 3. When the window open period is set to 75%, clearing the counter of the watchdog timer (writing ACH to
WDTE) must proceed outside the corresponding period from among those listed below, over which clearing
of the counter is prohibited (for example, confirming that the interval timer interrupt request flag (WDTIIF) of
the watchdog timer is set).
WDCS2
0
0
0
0
1
1
1
1
Remark f : Low-speed on-chip oscillator clock frequency
IL
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Watchdog timer overflow time
WDCS1 WDCS0
(f
6
2 /f (3.71 ms)
0 0
IL
7
2 /f (7.42 ms)
0 1 IL
8
2 /f (14.84 ms)
1 0
IL
9
2 /f (29.68 ms)
1 1 IL
11
2 /f (118.72 ms)
0 0
IL
13
2 /f (474.89 ms)
0 1 IL
14
2 /f (949.79 ms)
1 0
IL
16
2 /f (3799.18 ms)
1 1
IL
= 17.25 kHz (MAX.))
IL
CHAPTER 25 OPTION BYTE
Period over which clearing the
counter is prohibited when the
window open period is set to 75%
1.85 ms to 2.51 ms
3.71 ms to 5.02 ms
7.42 ms to 10.04 ms
14.84 ms to 20.08 ms
56.36 ms to 80.32 ms
237.44 ms to 321.26 ms
474.89 ms to 642.51 ms
1899.59 ms to 2570.04 ms
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