Renesas RL78 Series User Manual page 345

RL78/G1D
A/D Converter Mode
Register 0 (ADM0)
FR2 FR1 FR0 LV1 LV0
0 0 0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0 0 1
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Notes 1. For the second and subsequent conversion in sequential conversion mode, and for conversion of the channel
specified by scan 1, 2, and 3 in scan mode, the conversion start time and stabilization wait time for A/D power
supply do not occur after a hardware trigger is detected (see Table 12-3 (1/4)).
2. These are the numbers of clock cycles when conversion is with 10-bit resolution. When eight-bit resolution is
selected, the values are shorter by two cycles of the conversion clock (f
Cautions 1. The A/D conversion time must also be within the relevant range of conversion times (t
described in 30.7.1 A/D converter characteristics. Note that the conversion time (t
include the A/D power supply stabilization wait time.
2. Rewrite the FR2 to FR0, LV1 and LV0 bits to other than the same data while conversion is stopped
(ADCS = 0, ADCE = 0).
3. The above conversion time does not include conversion start time. Conversion start time add in the
first conversion. Select conversion time, taking clock frequency errors into consideration.
4. When hardware trigger wait mode, specify the conversion time, including the A/D power supply
stabilization wait time from the hardware trigger detection.
Remark f
: CPU/peripheral hardware clock frequency
CLK
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Table 12-3. A/D Conversion Time Selection (3/4)
(3) When there is A/D power supply stabilization wait time
Normal mode 1, 2 (hardware trigger wait mode
Mode Conversion Number of
Clock (f ) A/D Power
AD
Supply
Stabilization
Wait Clock
Normal f /64 8 f
CLK AD
1
f /32
CLK
f /16
CLK
f /8
CLK
f /6
CLK
f /5
CLK
f /4
CLK
f /2
CLK
Normal f /64 8 f
CLK AD
2
f /32
CLK
f /16
CLK
f /8
CLK
f /6
CLK
f /5
CLK
f /4
CLK
f /2
CLK
Number of A/D Power A/D Power Supply Stabilization Wait Time +
Conversion Supply
Note 2
Clock Stabilization
Wait Time +
f =
CLK
Conversion
1 MHz
Time
19 f 1728/f Setting
AD CLK
(number prohibited
of
864/f
CLK
sampling
432/f
CLK
clock:
216/f
CLK
7 f )
AD
162/f
CLK
135/f 135 µs
CLK
108/f 108 µs
CLK
54/f 54 µs
CLK
17 f 1600/f Setting
AD CLK
(number prohibited
of
800/f
CLK
sampling
400/f
CLK
clock:
200/f
CLK
5 f )
AD 150/f
CLK
125/f 125 µs
CLK
100/f 100 µs
CLK
50/f 50 µs
CLK
CHAPTER 12 A/D CONVERTER
Note 1
)
Conversion Time at 10-Bit Resolution
2.7 V ≤ V ≤ 3.6 V
DD
f = f = f
CLK CLK CLK
4 MHz 8 MHz 16 MHz
Setting Setting 108 µs
prohibited prohibited
108 µs
54 µs
108 µs
54 µs 27 µs
54 µs 27 µs 13.5 µs
40.5 µs 20.25 µs 10.125 µs
33.75 µs 16.875 µs 8.4375 µs
27 µs 13.5 µs 6.75 µs
13.5 µs 6.75 µs 3.375 µs
Setting Setting 100 µs
prohibited prohibited
100 µs 50 µs
100 µs 50 µs 25 µs
50 µs 25 µs 12.5 µs
37.5 µs 18.75 µs 9.375 µs
31.25 µs 15.625 µs 7.8125 µs
25 µs 12.5 µs 6.25 µs
12.5 µs 6.25 µs 3.125 µs
).
AD
= f =
CLK
32 MHz
54 µs
27 µs
13.5 µs
6.75 µs
5.0625 µs
4.21875 µs
3.375 µs
Setting
prohibited
50 µs
25 µs
12.5 µs
6.25 µs
4.6875 µs
3.90625 µs
3.125 µs
Setting
prohibited
)
CONV
) does not
CONV
324