Renesas RL78 Series User Manual page 83

RL78/G1D
Address Special Function Register (SFR) Name
F0010H A/D converter mode register 2
F0011H Conversion result comparison upper
limit setting register
F0012H Conversion result comparison lower
limit setting register
F0013H A/D test register
F0030H Pull-up resistor option register 0
F0031H Pull-up resistor option register 1
F0033H Pull-up resistor option register 3
F0034H Pull-up resistor option register 4
F003CH Pull-up resistor option register 12
F003EH Pull-up resistor option register 14
F0040H Port input mode register 0
F0041H Port input mode register 1
F0050H Port output mode register 0
F0051H Port output mode register 1
F0060H Port mode control register 0
F006CH Port mode control register 12
F0070H Noise filter enable register 0
F0071H Noise filter enable register 1
F0074H Timer input select register 0
F0076H A/D port configuration register
F0077H Peripheral I/O redirection register
F0078H Invalid memory access detection
control register
F007DH Global digital input disable register
F0090H Data flash control register
F00A0H High-speed on-chip oscillator trimming
register
F00A8H High-speed on-chip oscillator frequency
select register
F00E0H Multiplication/division data register C (L) MDCL
F00E2H Multiplication/division data register C
(H)
F00E8H Multiplication/division control register
F00F0H Peripheral enable register 0
F00F3H Subsystem clock supply mode control
register
F00F5H RAM parity error control register
F00FEH BCD adjust result register
Notes 1. The value after a reset is adjusted at the time of shipment.
2. The value after a reset is a value set in FRQSEL2 to FRQSEL0 of the option byte (000C2H).
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Table 4-6. Extended SFR (2nd SFR) List (1/5)
Symbol
ADM2
ADUL
ADLL
ADTES
PU0
PU1
PU3
PU4
PU12
PU14
PIM0
PIM1
POM0
POM1
PMC0
PMC12
NFEN0
NFEN1
TIS0
ADPC
PIOR
IAWCTL
GDIDIS
DFLCTL
HIOTRM
HOCODIV
MDCH
MDUC
PER0
OSMC
RPECTL
BCDADJ
CHAPTER 4 CPU ARCHITECTURE
R/W Manipulable Bit Range
1-bit 8-bit
R/W
 
R/W –

R/W –

R/W –

R/W
 
R/W
 
R/W
 
R/W
 
R/W
 
R/W
 
R/W
 
R/W
 
R/W
 
R/W
 
R/W
 
R/W
 
R/W
 
R/W
 
R/W –

R/W –

R/W –

R/W –

R/W
 
R/W
 
R/W –

R/W –

R/W – –
R/W – –
R/W
 
R/W
 
R/W –

R/W
 
R –

After Reset
16-bit
– 00H
– FFH
– 00H
– 00H
– 00H
– 00H
– 00H
– 01H
– 00H
– 00H
– 00H
– 00H
– 00H
– 00H
– FFH
– FFH
– 00H
– 00H
– 00H
– 00H
– 00H
– 00H
– 00H
– 00H
Note
– Undefined
1
Note
– Undefined
2
0000H

0000H

– 00H
– 00H
– 00H
– 00H
– Undefined
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