Renesas RL78 Series User Manual page 730

RL78/G1D
The status of the RESF register when a reset request is generated is shown in Table 20-3.
Table 20-3. RESF Register Status When Reset Request Is Generated
Reset Source RESET Input
Flag
TRAP bit Cleared (0)
WDTRF bit
RPERF bit
IAWRF bit
LVIRF bit
The RESF register is automatically cleared when it is read by an 8-bit memory manipulation instruction. Figure 20-5
shows the procedure for checking a reset source.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Reset by Reset by
POR Execution of
Illegal
Instruction
Cleared (0) Set (1)
Held
CHAPTER 20 RESET FUNCTION
Reset by Reset by
WDT RAM parity
error
Held Held
Set (1)
Held Set (1)
Held
Reset by Reset by
illegal- LVD
memory
access
Held Held
Set (1)
Held Set (1)
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