Renesas RL78 Series User Manual page 148

RL78/G1D
Address: F00F0H
Symbol <7>
PER0 RTCEN
IICA0EN
0
1
SAU1EN
0
1
SAU0EN
0
1
TAU0EN
0
1
Caution Be sure to clear bits 1 and 6 to "0"
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 6-7. Format of Peripheral Enable Register 0 (PER0) (2/2)
After reset: 00H R/W
6 <5>
0 ADCEN
Control of serial interface IICA0 input clock supply
Stops input clock supply.
● SFR used by the serial interface IICA0 cannot be written.
● The serial interface IICA0 is in the reset status.
Enables input clock supply.
● SFR used by the serial interface IICA0 can be read and written.
Stops input clock supply.
● SFR used by the serial array unit 1 cannot be written.
● The serial array unit 1 is in the reset status.
Enables input clock supply.
● SFR used by the serial array unit 1 can be read and written.
Stops input clock supply.
● SFR used by the serial array unit 0 cannot be written.
● The serial array unit 0 is in the reset status.
Enables input clock supply.
● SFR used by the serial array unit 0 can be read and written.
Stops input clock supply.
● SFR used by timer array unit 0 cannot be written.
● Timer array unit 0 is in the reset status.
Enables input clock supply.
● SFR used by timer array unit 0 can be read and written.
<4> <3>
IICA0EN SAU1EN
Control of serial array unit 1 input clock supply
Control of serial array unit 0 input clock supply
Control of timer array unit 0 input clock supply
CHAPTER 6 CLOCK GENERATOR
<2> 1
SAU0EN 0
<0>
TAU0EN
127