Renesas RL78 Series User Manual page 526

RL78/G1D
Figure 13-100. Flowchart of Simplified I
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Tra nsmitt ing address field
Default setting
Writing 0 to the SOmn bit
Wait
Writing 0 to the CKOmn bit
Writing 1 to the SOEmn bit
Writing 1 to the SSmn bit
Writing address and R/W
data to SIOr (SDRmn[7:0])
Transfer end interrupt
generated?
Yes
Responded ACK?
Yes
Address field
transmission completed
To data transmission flow
and data reception flow
CHAPTER 13 SERIAL ARRAY UNIT
2
C Address Field Transmission
For the initial setting, refer to Figure 13-96
Set the SOmn bit to 0
Start condition generate
To secure a hold time of SCL signal
Prepare to communicate the SCL signal is
fall
Enable serial output
To serial operation enable status
Transmitting address field
Wait for address field transmission
complete.
No
(Clear the interrupt request flag)
ACK response from the slave
will be confirmed in PEFmn bit.
if ACK (PEFmn = 0), to the next
No
processing, if NACK (PEFmn =
1) to error processing.
Communication error
processing
505