Renesas RL78 Series User Manual page 166

RL78/G1D
Table 6-3. CPU Clock Transition and SFR Register Setting Examples (4/5)
(9) CPU clock changing from subsystem clock (D) to high-speed system clock (C)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(D) → (C) (X1 clock: 1 MHz ≤ f
MHz)
(D) → (C) (X1 clock: 10 MHz < f
MHz)
(D) → (C) (external main clock)
Note Set the oscillation stabilization time as follows.
● Desired the oscillation stabilization time counter status register (OSTC) oscillation stabilization time
Oscillation stabilization time set by the oscillation stabilization time select register (OSTS)
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
CHAPTER 30 ELECTRICAL SPECIFICATIONS).
(10) ● HALT mode (E) set while CPU is operating with high-speed on-chip oscillator clock (B)
● HALT mode (F) set while CPU is operating with high-speed system clock (C)
● HALT mode (G) set while CPU is operating with subsystem clock (D)
Status Transition
(B) → (E)
(C) → (F)
(D) → (G)
Remark (A) to (J) in Table 6-3 correspond to (A) to (J) in Figure 6-16.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
OSTS
Register
≤ 10 Note
X
≤ 20 Note
X
Note
Unnecessary if the CPU is operating with the high-speed system clock
Executing HALT instruction
CHAPTER 6 CLOCK GENERATOR
CSC Register
MSTOP
0 Must be checked
0 Must be checked
0 Must not be checked
Setting
OSTC Register CKC Register
CSS
0
0
0
≤
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