Renesas RL78 Series User Manual page 97

RL78/G1D
word [BC]
<1> <2>
Instruction code
OP-code
Low Addr.
<1>
High Addr.
"word" <1> specifies the address where the target
array of word-sized data starts in the 64-Kbyte area
from F0000H to FFFFFH.
A pair of registers <2> specifies an offset within
the array to the target location in memory.
ES: [HL + byte], ES: [DE + byte]
<1> <2>
Instruction code
OP-code
byte
<3>
The ES register <1> specifies a 64-Kbyte
area within the overall 1-Mbyte space as
the four higher-order bits, X, of the address range.
Either pair of registers <2> specifies the address
where the target array of data starts in the 64-Kbyte
area specified in the ES register <1>.
"byte" <3> specifies an offset within the array to the
target location in memory.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 4-30. Example of word[BC]
<2>
<2>
rp(BC)
Address of a word
<1>
within an array
Figure 4-31. Example of ES:[HL + byte], ES:[DE + byte]
<3> <1> <2> <3>
<2>
rp(HL/DE)
<1>
ES
CHAPTER 4 CPU ARCHITECTURE
Target memory
Offset
Memory
<3> Target memory
Offset
<2> Address of
an array
X0000H
Specifies a
<1>
64-Kbyte area
FFFFFH
Array of
word-sized
data
F0000H
XFFFFH
Target
array
of data
Other data in
the array
X0000H
Memory
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