Renesas RL78 Series User Manual page 620

16-bit single-chip microcontrollers

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Table of Contents

(8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (1/3)

(ACK detection)

(8 or 9 clock wait)

(ACK control)

(communication status)

(ST trigger)

(SP trigger)

(wait cancellation)

(transmit/receive)

(clock line)

(ACK detection)

(ST detection)

(SP detection)

(8 or 9 clock wait)

(ACK control)

(communication status)

(wait cancellation)

(transmit/receive)

: Wait state by master device

Notes 1. For releasing wait state during reception of a master device, write "FFH" to IICAn or set the WRELn bit.

2. Make sure that the time between the fall of the SDAAn pin signal and the fall of the SCLAn pin signal is

at least 4.0 µs when specifying standard mode and at least 0.6 µs when specifying fast mode.

3. Write data to IICAn, not setting the WRELn bit, in order to cancel a wait state during transmission by a

slave device.

Remark n = 0

R01UH0515EJ0120 Rev.1.20

Dec 16, 2016

Figure 14-33. Example of Slave to Master Communication

(a) Start condition ~ address ~ data

Start condition

: Wait state by slave device

CHAPTER 14 SERIAL INTERFACE IICA

Slave address

: Wait state by master and slave devices

Rl78/g1d R5f11agg R5f11agh R5f11agj