Renesas RL78 Series User Manual page 729

16-bit single-chip microcontrollers

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20.3 Register for Confirming Reset Source

20.3.1 Reset control flag register (RESF)

Many internal reset generation sources exist in the RL78 microcontroller. The reset control flag register (RESF) is used

to store which source has generated the reset request.

The RESF register can be read by an 8-bit memory manipulation instruction.

RESET input, reset by power-on-reset (POR) circuit, and reading the RESF register clear TRAP, WDTRF, RPERF,

IAWRF, and LVIRF flags.

Address: FFFA8H

The value after reset varies depending on the reset source. See Table 20-3.

The illegal instruction is generated when instruction code FFH is executed.

Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip

debug emulator.

Cautions 1. Do not read data by a 1-bit memory manipulation instruction.

2. When enabling RAM parity error resets (RPERDIS = 0), be sure to initialize the used RAM area

at data access or the used RAM area + 10 bytes at execution of instruction from the RAM area.

Reset generation enables RAM parity error resets (RPERDIS = 0). For details, see 23.3.3 RAM

parity error detection function.

R01UH0515EJ0120 Rev.1.20

Dec 16, 2016

Figure 20-4. Format of Reset Control Flag Register (RESF)

After reset: Undefined

Internal reset request by execution of illegal instruction