Renesas RL78 Series User Manual page 568

16-bit single-chip microcontrollers

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The wait is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive

data (i.e., is in a wait state).

Setting the SCLAn pin to low level notifies the communication partner of the wait state. When wait state has been

canceled for both the master and slave devices, the next data transfer can begin.

(a) When master device has a nine-clock wait and slave device has an eight-clock wait

Transfer lines

Remark n = 0

R01UH0515EJ0120 Rev.1.20

Dec 16, 2016

Figure 14-20. Wait (1/2)

(master transmits, slave receives, and ACKEn = 1)

Master returns to high

impedance but slave

is in wait state (low level).

Wait after output

of eighth clock

CHAPTER 14 SERIAL INTERFACE IICA

Wait after output

of ninth clock

FFH is written to IICAn or WRELn is set to 1

Wait from slave

Wait from master

IICA0 data write (cancel wait)

Rl78/g1d R5f11agg R5f11agh R5f11agj