Renesas RL78 Series User Manual page 649

RL78/G1D
16.2.3 Multiplication/division data register C (MDCL, MDCH)
The MDCH and MDCL registers are used to store the accumulated result while in the multiply-accumulator mode or the
remainder of the operation result while in the division mode. These registers are not used while in the multiplication mode.
The MDCH and MDCL registers can be set by a 16-bit manipulation instruction.
Reset signal generation clears these registers to 0000H.
Figure 16-4. Format of Multiplication/Division Data Register C (MDCH, MDCL)
Address: F00E0H, F00E1H, F00E2H, F00E3H
Symbol
MDCH MDCH MDCH
15 14
Symbol
MDCL MDCL MDCL
15 14
Cautions 1. The MDCH and MDCL registers values read during division operation processing (when the
multiplication/division control register (MDUC) value is 81H or C1H) will not be guaranteed.
2. During multiply-accumulator processing, do not use software to rewrite the values of the
MDCH and MDCL registers. If this is done, the operation result will be undefined.
3. The data is in the two's complement format in the multiply-accumulator mode (signed).
Table 16-4. Functions of MDCH and MDCL Registers During Operation Execution
Operation Mode
Multiplication mode (unsigned
or signed)
Multiply-accumulator mode
(unsigned)
Multiply-accumulator mode
(signed)
Division mode (unsigned)
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
CHAPTER 16 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR
After reset: 0000H, 0000H R/W
F00E3H
MDCH MDCH MDCH MDCH
13 12 11 10
F00E1H
MDCL MDCL MDCL MDCL
13 12 11 10
Setting
MDCH: Initial accumulated value (unsigned)
(higher 16 bits)
MDCL: Initial accumulated value (unsigned)
(lower 16 bits)
MDCH: Initial accumulated value (signed)
(higher 16 bits)
MDCL: Initial accumulated value (signed)
(lower 16 bits)
MDCH MDCH MDCH MDCH
9 8 7 6
MDCL MDCL MDCL MDCL
9 8 7 6
–
MDCH: accumulated value (unsigned)
MDCL: accumulated value (unsigned)
MDCH: accumulated value (signed)
MDCL: accumulated value (signed)
– MDCH: Remainder (unsigned)
MDCL: Remainder (unsigned)
F00E2H
MDCH MDCH MDCH MDCH
5 4 3 2
F00E0H
MDCL MDCL MDCL MDCL
5 4 3 2
Operation Result
–
(higher 16 bits)
(lower 16 bits)
(higher 16 bits)
(lower 16 bits)
(higher 16 bits)
(lower 16 bits)
MDCH MDCH
1 0
MDCL MDCL
1 0
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