Renesas RL78 Series User Manual page 362

RL78/G1D
12.6.2 Software trigger mode (select mode, one-shot conversion mode)
<1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the
A/D conversion standby status.
<2> After the software counts up to the stabilization wait time (1 µs), the ADCS bit of the ADM0 register is set to 1 to
perform the A/D conversion of the analog input specified by the analog input channel specification register (ADS).
<3> When A/D conversion ends, the conversion result is stored in the A/D conversion result register (ADCR, ADCRH),
and the A/D conversion end interrupt request signal (INTAD) is generated.
<4> After A/D conversion ends, the ADCS bit is automatically cleared to 0, and the system enters the A/D conversion
standby status.
<5> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially converted data is discarded.
<6> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the analog input respecified by the ADS register.
The partially converted data is discarded.
<7> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the
system enters the A/D conversion standby status.
<8> When ADCE is cleared to 0 while in the A/D conversion standby status, the A/D converter enters the stop status.
When ADCE = 0, specifying 1 for ADCS is ignored and A/D conversion does not start.
conversion does not start even if a hardware trigger is input while in the A/D conversion standby status.
Figure 12-18. Example of Software Trigger Mode (Select mode, One-Shot Conversion Mode) Operation Timing
<1> ADCE is set to 1.
ADCE
ADCS is set to
<2>
1 while in the
The trigger
conversion
is not
standby status.
acknowledged.
ADCS
Data 0
ADS
(ANI0)
A/D
Stop Conversion
Data 0
conversion
status standby
(ANI0)
status
ADCR,
ADCRH
INTAD
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
ADCS is
ADCS is overwritten
<4> automatically <2> <5>
with 1 during A/D
cleared to
conversion operation.
0 after
conversion
ends.
Conversion is
A/D
<3>
interrupted
conversion
and restarts.
ends.
Conversion
Data 0 Data 0
standby
(ANI0) (ANI0)
Data 0
(ANI0)
<4> <2>
<6> ADS is rewritten during
A/D conversion operation
(from ANI0 to ANI1).
Data 1
(ANI1)
<3>
Conversion
Data 0 Data 1
standby
(ANI0) (ANI1)
Data 0
(ANI0)
CHAPTER 12 A/D CONVERTER
In addition, A/D
ADCE is cleared to 0. <8>
ADCS is
<7>
<4> <2>
cleared to
0 during A/D
conversion
operation.
Conversion is
<3>
interrupted.
Conversion
Conversion
Data 1
standby
standby
(ANI1)
Data 1
(ANI1)
The trigger
is not
acknowledged.
Stop
status
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