Renesas RL78 Series User Manual page 381

RL78/G1D
Normal
operation
STOP
mode
SNOOZE
mode
The clock request signal
(an internal signal) is
automatically set to the low
level in the SNOOZE mode.
Normal
operation
Notes 1. If the A/D conversion end interrupt request signal (INTAD) is not generated by setting ADRCK bit and
ADUL/ADLL register, the result is not stored in the ADCR and ADCRH registers.
The system enters the STOP mode again. If a hardware trigger is input later, A/D conversion operation is
again performed in the SNOOZE mode.
2. If the AWC bit is left set to 1, A/D conversion will not start normally in spite of the subsequent SNOOZE or
normal operation mode. Be sure to clear the AWC bit to 0.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 12-37. Flowchart for Setting up SNOOZE Mode
Start of setup
The ADCEN bit of the PER0 register is set (1), and supplying the clock starts.
PER0 register setting
The ports are set to analog input.
ADPC and PMCx
ANI0 to ANI3 pins: Set using theADPC register
register settings
ANI16 to ANI19 pins: Set using the PMCx register
The ports are set to the input mode.
PMx register setting
• ADM0 register
FR2 to FR0, LV1, and LV0 bits: These are used to specify theA/D conversion time.
ADMD bit: Select mode/scan mode
• ADM0 register setting
• ADM1 register
ADTMD1 and ADTMD0 bits: These are used to specify the hardware trigger wait mode.
• ADM1 register setting
ADSCM bit: One-shot conversion mode
• ADM2 register setting ADTRS1 and ADTRS0 bits: These are used to select the hardware trigger signal.
• ADM2 register
• ADUL/ADLL register
ADREFP1, ADREFP0, and ADREFM bits: These are used to select the reference voltage.
setting
ADRCK bit: This is used to select the range for theA/D conversion result comparison value
generated by the interrupt signal fromAREA1, AREA3, and AREA2.
• ADS register setting
ADTYP bit: 8-bit/10-bit resolution
(The order of the settings • ADUL/ADLL register
is irrelevant.)
These are used to specify the upper limit and lower limitA/D conversion result comparison values
• ADS register
ADS4 to ADS0 bits: These are used to select the analog input channels.
The reference voltage stabilization wait time A indicated by A below may be required if the values
Reference voltage
of the ADREFP1 and ADREFP0 bits are changed.
stabilization wait time count A
If the values ofADREFP1 and ADREFP0 are changed to 1 and 0, respectively: A = 5 µs
A wait is not required if the values ofADREFP1 and ADREFP0 are changed to 0 and 0 or 0 and 1,
respectively.
AWC = 1 Immediately before entering the S TOP mode, enable the SNOOZE mode by setting theAWC bit of
the ADM2 register to 1.
The ADCE bit of the ADM0 register is set (1), and the system enters theA/D conversion
ADCE bit setting
standby status.
Enter the STOP mode
After hardware trigger is generated, the system automatically counts up to the stabilization
Hardware trigger
wait time for A/D power supply andA/D conversion is started in the SNOOZE mode.
generation
The A/D conversion
operations are performed.
The A/D conversion end interrupt (INTAD) is generated.
End of A/D conversion
No
INTAD
generation
Yes
Storage of conversion The conversion results are stored in theADCR and ADCRH registers.
results in the ADCR and
ADCRH registers
AWC = 0 Release the SNOOZE mode by clearing theAWC bit of the ADM2 register to 0.
Normal operation
CHAPTER 12 A/D CONVERTER
Note1
Note2
360