Renesas RL78 Series User Manual page 482

RL78/G1D
(2) SNOOZE mode operation (continuous startup)
Figure 13-72. Timing Chart of SNOOZE Mode Operation (continuous startup) (Type 1: DAPmn = 0, CKPmn = 0)
CPU operation status Normal operation STOP mode
<3>
SS00
<1>
ST00
SE00
SWC0
SSEC0 L
Clock request signal
(internal signal)
SDR00
SCK00 pin
SI00 pin
Shift register 00
INTCSI00
TSF00
Note Only read received data while SWCm = 1 and before the next valid edge of the SCKp pin input is detected.
Cautions 1. Before switching to the SNOOZE mode or after reception operation in the SNOOZE mode
finishes, set the STm0 bit to 1 (clear the SEm0 bit and stop the operation). After the receive
operation completes, also clear the SWCm bit to 0 (SNOOZE mode release).
2. When SWCm = 1, the BFFm0 and OVFm0 flags will not change.
Remarks 1. <1> to <10> in the figure correspond to <1> to <10> in Figure 13-73 Flowchart of SNOOZE Mode
Operation (continuous startup).
2. m = 0; p = 00
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
SNOOZE mode
<4>
Reception & shift operation
Data reception
<2>
<5><6>
Normal operation
<3>
<9>
<10>
Note
Read
<8>
Receive data 1
<7>
CHAPTER 13 SERIAL ARRAY UNIT
STOP mode SNOOZE mode
<4>
Receive data 1
Receive data 2
Reception & shift operation
Data reception
<2> <5><6>
Receive data 2
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