Renesas RL78 Series User Manual page 320

RL78/G1D
Figure 10-1. Block Diagram of Clock Output/Buzzer Output Controller
f
MAIN
Prescaler
5
f
Prescaler
SUB
PCLOE0 0
Note For output frequencies available from PCLBUZ0, see 30.6 AC Characteristics.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
3
11 13
f /2 to f /2
MAIN MAIN
4
f to f /2
MAIN MAIN
7
f to f /2
SUB SUB
8
0 0 CSEL0 CCS02 CCS01 CCS00
Clock output select register 0 (CKS0)
Internal bus
Clock/buzzer
controller
PCLOE0
Output latch
PM140
(P140)
Note
PCLBUZ0 /INTP6/P140
299