Renesas RL78 Series User Manual page 614

RL78/G1D
(9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (2/4)
Master side
IICAn
ACKDn
(ACK detection)
WTIMn
(8 or 9 clock wait)
ACKEn
(ACK control)
MSTSn
(communication status)
STTn
(ST trigger)
SPTn
(SP trigger)
WRELn
(wait cancellation)
INTIICAn
(interrupt)
TRCn
(transmit/receive)
Bus line
SCLAn (bus)
(clock line)
SDAAn (bus)
(data line)
Slave side
IICAn
ACKDn
(ACK detection)
STDn
(ST detection)
SPDn
(SP detection)
WTIMn
(8 or 9 clock wait)
ACKEn
(ACK control)
MSTSn
(communication status)
WRELn
(wait cancellation)
INTIICAn
(interrupt)
TRCn
(transmit/receive)
: Wait state by slave device
Notes 1. Write data to IICAn, not setting the WRELn bit, in order to cancel a wait state during transmission by a
master device.
2. For releasing wait state during reception of a slave device, write "FFH" to IICAn or set the WRELn bit.
Remark n = 0
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 14-32. Example of Master to Slave Communication
(b) Address ~ data ~ data
Note 1
<5>
H
H
H
L
L
L
H
<4>
W ACK
D 7
D
1
<3>
L
H
H
L
<6> Note 2
L
CHAPTER 14 SERIAL INTERFACE IICA
6 D 5 D 4 D 3 D 2
1 1 1 1 1
: Wait state by master and slave devices
Note 1
<9>
<8>
ACK
D 1 D 0
1 1
<7>
<10>
D 7
2
Note 2
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