Renesas RL78 Series User Manual page 759

RL78/G1D
<Operation flow>
<R> Figure 23-3. Flowchart of Flash Memory CRC Operation Function (High-speed CRC)
Cautions 1. The CRC operation is executed only on the code flash.
2. Store the expected CRC operation value in the area below the operation range in the code
3. The CRC operation is enabled by executing the HALT instruction in the RAM area.
The expected CRC value can be calculated by using the Integrated Development Environment CubeSuite+. See the
Integrated Development Environment CubeSuite+ user's manual for details.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Start
Set FEA5 to FEA0 bits
Copy HALT and RET instructions to
RAM, initialize 10 bytes
All xxMKx = 1
CRC0EN = 1
PGCRCL = 0000H
Execute CALL instruction
Execute HALT instruction.
CRC operation
completed?
Yes
Execute RET instruction.
CRC0EN = 0
Read the value of PGCRCL.
Compare the value with
the expected CRC value.
Match
Correctly complete
flash.
Be sure to execute the HALT instruction in RAM area.
CHAPTER 23 SAFETY FUNCTIONS
; Store the expected CRC operation result
; value in the lowest 4 bytes.
; Set CRC operation range.
; Copy the HALT and RET instructions to the
; RAM to execute in the RAM.
; Initialize the 10 bytes after the RET instruction.
; Masks all interrupt
; Enable CRC operation
; Initialize the CRC operation result register
; Call the address of the HALT instruction
; copied to the RAM.
; CRC operation starts by HALT instruction
; execution
No
; When the CRC operation is complete, the HALT
; mode is released and control is returned from RAM
; Prohibit CRC operation
; Read CRC operation result
; Compare the value with the stored expected
; value.
Not match
Abnormal complete
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