Renesas RL78 Series User Manual page 266

RL78/G1D
Figure 7-68. Operation Procedure of One-Shot Pulse Output Function (1/2)
TAU
default
setting
Sets the TAUmEN bit of peripheral enable registers 0
(PER0) to 1.
Sets timer clock select register m (TPSm).
Determines clock frequencies of CKm0 and CKm1.
Channel Sets the corresponding bit of noisefilter enable register 1
default (NFEN1) to 1.
setting Sets timer mode register mn, mp (TMRmn, TMRmp) of
two channels to be used (determines operation mode of
channels).
An output delay is set to timer data register mn (TDRmn)
of the master channel, and a pulse width is set to the
TDRmp register of the slave channel.
Sets slave channel.
The TOM0p bit of timer output mode register 0 (TOM0)
is set to 1 (slave channel output mode).
Sets the TOL0p bit.
Sets the TO0p bit and determines default level of the
TO0p output.
Sets the TOE0p bit to 1 and enables operation of TO0p.
Clears the port register and port mode register to 0.
(Remark is listed on the next page.)
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Software Operation
CHAPTER 7 TIMER ARRAY UNIT
Hardware Status
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Channel stops operating.
(Clock is supplied and some power is consumed.)
The TO0p pin goes into Hi-Z output state.
The TO0p default setting level is output when the port
mode register is in output mode and the port register is 0.
TO0p does not change because channel stops operating.
The TO0p pin outputs the TO0p set level.
245