Renesas RL78 Series User Manual page 555

RL78/G1D
ACKDn
0
1
Condition for clearing (ACKDn = 0)
● When a stop condition is detected
● At the rising edge of the next byte's first clock
● Cleared by LRELn = 1 (exit from communications)
● When the IICEn bit changes from 1 to 0 (operation
stop)
● Reset
STDn
0
1
Condition for clearing (STDn = 0)
● When a stop condition is detected
● At the rising edge of the next byte's first clock
following address transfer
● Cleared by LRELn = 1 (exit from communications)
● When the IICEn bit changes from 1 to 0 (operation
stop)
● Reset
SPDn
0
1
Condition for clearing (SPDn = 0)
● At the rising edge of the address transfer byte's first
clock following setting of this bit and detection of a
start condition
● When the WUPn bit changes from 1 to 0
● When the IICEn bit changes from 1 to 0 (operation
stop)
● Reset
Remarks 1.
14.3.4 IICA flag register n (IICFn)
This register sets the operation mode of I
The IICFn register can be set by a 1-bit or 8-bit memory manipulation instruction. However, the STTn clear flag
2
(STCFn) and I C bus status flag (IICBSYn) bits are read-only.
The IICRSVn bit can be used to enable/disable the communication reservation function.
The STCENn bit can be used to set the initial value of the IICBSYn bit.
The IICRSVn and STCENn bits can be written only when the operation of I
register n0 (IICCTLn0) = 0). When operation is enabled, the IICFn register can be read.
Reset signal generation clears this register to 00H.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 14-7. Format of IICA Status Register n (IICSn) (3/3)
Acknowledge was not detected.
Acknowledge was detected.
Start condition was not detected.
Start condition was detected. This indicates that the address transfer period is in effect.
Stop condition was not detected.
Stop condition was detected. The master device's communication is terminated and the bus is
released.
LRELn: Bit 6 of IICA control register n0 (IICCTLn0)
IICEn: Bit 7 of IICA control register n0 (IICCTLn0)
2. n = 0
2
C and indicates the status of the I
CHAPTER 14 SERIAL INTERFACE IICA
Detection of acknowledge (ACK)
Condition for setting (ACKDn = 1)
● After the SDAAn line is set to low level at the rising
edge of SCLAn line's ninth clock
Detection of start condition
Condition for setting (STDn = 1)
● When a start condition is detected
Detection of stop condition
Condition for setting (SPDn = 1)
● When a stop condition is detected
2
C bus.
2
C is disabled (bit 7 (IICEn) of IICA control
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