Renesas RL78 Series User Manual page 880

RL78/G1D
Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected.
2. The maximum value (MAX.) of t
(acknowledge) timing.
Caution The values in the above table are applied even when bit 2 (PIOR2) in the peripheral I/O redirection
register (PIOR) is 1. At this time, the pin characteristics (I
the redirect destination.
Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up
resistor) at that time in each mode are as follows.
Standard mode: C
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
is during normal transfer and a wait state is inserted in the ACK
HD:DAT
= 400 pF, R = 2.7 kΩ
b b
CHAPTER 30 ELECTRICAL SPECIFICATIONS
, I , V , V
OH1 OL1 OH1 OL1
) must satisfy the values in
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