Renesas RL78 Series User Manual page 365

RL78/G1D
12.6.5 Hardware trigger no-wait mode (select mode, sequential conversion mode)
<1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the
A/D conversion standby status.
<2> After the software counts up to the stabilization wait time (1 µs), the ADCS bit of the ADM0 register is set to 1 to
place the system in the hardware trigger standby status (and conversion does not start at this stage). Note that,
while in this status, A/D conversion does not start even if ADCS is set to 1.
<3> If a hardware trigger is input while ADCS = 1, A/D conversion is performed on the analog input specified by the
analog input channel specification register (ADS).
<4> When A/D conversion ends, the conversion result is stored in the A/D conversion result register (ADCR, ADCRH),
and the A/D conversion end interrupt request signal (INTAD) is generated. After A/D conversion ends, the next
A/D conversion immediately starts.
<5> If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially converted data is discarded.
<6> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the analog input respecified by the ADS register.
The partially converted data is discarded.
<7> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially converted data is discarded.
<8> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the
system enters the A/D conversion standby status. However, the A/D converter does not stop in this status.
<9> When ADCE is cleared to 0 while in the A/D conversion standby status, the A/D converter enters the stop status.
When ADCS = 0, inputting a hardware trigger is ignored and A/D conversion does not start.
Figure 12-21. Example of Hardware Trigger No-Wait Mode (Select mode, Sequential Conversion Mode) Operation
<1>
ADCE is set to 1.
ADCE
<2> ADCS is set to 1.
<3>
Hardware
trigger
Trigger
The trigger is not standby
status
acknowledged.
ADCS
ADS
A/D
Stop Conversion
conversion
status standby
status
ADCR,
ADCRH
INTAD
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
<5>
A hardware trigger
is generated.
Data 0
(ANI0)
<4> A/D conversion
ends and the next
conversion
<4>
starts.
Data 0
Data 0 Data 0
(ANI0)
(ANI0) (ANI0)
Data 0 Data 0
(ANI0) (ANI0)
Timing
A hardware trigger is
generated during A/D
conversion operation.
ADCS is overwritten
with 1 during A/D
conversion operation.
ADS is rewritten during
<6>
A/D conversion operation
(from ANI0 to ANI1).
Conversion is Conversion is
interrupted <4> interrupted
and restarts. and restarts.
Data 1
Data 0 Data 0
(ANI0) (ANI1)
(ANI0)
Data 0
(ANI0)
CHAPTER 12 A/D CONVERTER
ADCE is cleared to 0. <9>
ADCS is cleared
<8>
<7>
to 0 during A/D
conversion operation.
Data 1
(ANI1)
Conversion is
interrupted and
restarts. is interrupted.
<4>
<4>
Data 1 Data 1
Data 1 Conversion
(ANI1) (ANI1)
(ANI1)
Data 1
(ANI1)
The trigger is not
acknowledged.
Conversion
Stop
status
standby
Data 1
(ANI1)
344