Renesas RL78 Series User Manual page 572

RL78/G1D
14.5.9 Address match detection method
2
In I C bus mode, the master device can select a particular slave device by transmitting the corresponding slave
address.
Address match can be detected automatically by hardware. An interrupt request (INTIICAn) occurs when the address
set to the slave address register n (SVAn) matches the slave address sent by the master device, or when an extension
code has been received.
14.5.10 Error detection
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In I C bus mode, the status of the serial data bus (SDAAn) during data transmission is captured by the IICA shift
register n (IICAn) of the transmitting device, so the IICA data prior to transmission can be compared with the transmitted
IICA data to enable detection of transmission errors. A transmission error is judged as having occurred when the
compared data values do not match.
14.5.11 Extension code
(1) When the higher 4 bits of the receive address are either "0000" or "1111", the extension code reception flag (EXCn)
is set to 1 for extension code reception and an interrupt request (INTIICAn) is issued at the falling edge of the
eighth clock. The local address stored in the slave address register n (SVAn) is not affected.
(2) The settings below are specified if 11110xx0 is transferred from the master by using a 10-bit address transfer when
the SVAn register is set to 11110xx0. Note that INTIICAn occurs at the falling edge of the eighth clock.
● Higher four bits of data match: EXCn = 1
● Seven bits of data match:
Remark EXCn: Bit 5 of IICA status register n (IICSn)
COIn: Bit 4 of IICA status register n (IICSn)
(3) Since the processing after the interrupt request occurs differs according to the data that follows the extension code,
such processing is performed by software.
If the extension code is received while a slave device is operating, then the slave device is participating in
communication even if its address does not match.
For example, after the extension code is received, if you do not wish to operate the target device as a slave device,
set bit 6 (LRELn) of IICA control register n0 (IICCTLn0) to 1 to set the standby mode for the next communication
operation.
Slave Address
0 0 0 0 0 0 0
1 1 1 1 0 x x
1 1 1 1 0 x x
Remarks 1. See the I
than those described above.
2. n = 0
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
COIn = 1
Table 14-3. Bit Definitions of Major Extension Codes
R/W Bit
0 General call address
0 10-bit slave address specification (during address authentication)
1 10-bit slave address specification (after address match, when read
command is issued)
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C bus specifications issued by NXP Semiconductors for details of extension codes other
CHAPTER 14 SERIAL INTERFACE IICA
Description
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