Renesas RL78 Series User Manual page 592

RL78/G1D
(b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart)
(i) When WTIMn = 0
ST AD6 to AD0 R/W ACK
1: IICSn = 1000×110B
2: IICSn = 1000×000B (Sets the WTIMn bit to 1)
3: IICSn = 1000××00B (Clears the WTIMn bit to 0
4: IICSn = 1000×110B
5: IICSn = 1000×000B (Sets the WTIMn bit to 1)
6: IICSn = 1000××00B (Sets the SPTn bit to 1)
7: IICSn = 00000001B
Notes 1. To generate a start condition, set the WTIMn bit to 1 and change the timing for generating the
INTIICAn interrupt request signal.
2. Clear the WTIMn bit to 0 to restore the original setting.
3. To generate a stop condition, set the WTIMn bit to 1 and change the timing for generating the
INTIICAn interrupt request signal.
Remark : Always generated
: Generated only when SPIEn = 1
×: Don't care
(ii) When WTIMn = 1
ST AD6 to AD0 R/W ACK
1: IICSn = 1000×110B
2: IICSn = 1000××00B (Sets the STTn bit to 1)
3: IICSn = 1000×110B
4: IICSn = 1000××00B (Sets the SPTn bit to 1)
5: IICSn = 00000001B
Remark : Always generated
: Generated only when SPIEn = 1
×: Don't care
Remark n = 0
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
STTn = 1
↓
D7 to D0 ACK ST
1 2 3
Note 1
Note 2
, sets the STTn bit to 1)
Note 3
STTn = 1
↓
D7 to D0 ACK ST AD6 to AD0
1 2
CHAPTER 14 SERIAL INTERFACE IICA
AD6 to AD0 R/W ACK
4
R/W ACK D7 to D0
3
SPTn = 1
↓
D7 to D0 ACK SP
7
6
5
SPTn = 1
↓
ACK SP
4 5
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