Renesas RL78 Series User Manual page 752

RL78/G1D
When setting an interrupt and reset mode (LVIMDS1, LVIMDS0 = 1, 0), voltage detection stabilization wait time for 400
µs or 5 clocks of f is necessary after LVD reset is released (LVIRF = 1). After waiting until voltage detection stabilizes,
IL
(0) clear the LVIMD bit for initialization. While voltage detection stabilization wait time is being counted and when the
LVIMD bit is rewritten, set LVISEN to 1 to mask a reset or interrupt generation by LVD.
Figure 22-9 shows the procedure for initial setting of interrupt and reset mode.
Remark f : Low-speed on-chip oscillator clock frequency
IL
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 22-9. Initial Setting of Interrupt and Reset Mode
Power application
Check reset source
No
LVIRF = 1 ?
Yes
LVISEN = 1
Voltage detection stabilization
wait time
LVIMD = 0
LVISEN = 0
Normal operation
CHAPTER 22 VOLTAGE DETECTOR
See Figure 19-5 Procedure for Checking Reset Resource.
Check internal reset generation by LVD circuit
Set the LVISEN bit to 1 to mask voltage detection
(LVIOMSK = 1)
µ
Count 400 s or 5 clocks of f
Set the LVIMD bit to 0 to set interrupt mode.
Set the LVISEN bit to 0 to enable voltage detection.
by software.
IL
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