Renesas RL78 Series User Manual page 767

RL78/G1D
Note The following table lists the code flash memory, RAM, and lowest detection address for each product:
Products
R5F11AGG
R5F11AGH
R5F11AGJ
23.3.6.1 Invalid memory access detection control register (IAWCTL)
This register is used to control the detection of invalid memory access and RAM/SFR guard function.
IAWEN bit is used in invalid memory access detection function.
The IAWCTL register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 23-12. Format of Invalid Memory Access Detection Control Register (IAWCTL)
Address: F0078H After reset: 00H
Symbol 7
IAWCTL IAWEN
Note
IAWEN
0
1
Note Only writing 1 to the IAWEN bit is enabled, not writing 0 to it after setting it to 1.
Remark By specifying WDTON = 1 (watchdog timer operation enable) for the option byte (000C0H), the invalid
memory access function is enabled even IAWEN = 0.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Code flash memory
(00000H to xxxxxH)
131072 × 8 bit
(00000H to 1FFFFH)
196608 × 8 bit
(00000H to 2FFFFH)
262144 × 8 bit
(00000H to 3FFFFH)
R/W
6 5
0 GRAM1
Disable the detection of invalid memory access.
Enable the detection of invalid memory access.
CHAPTER 23 SAFETY FUNCTIONS
RAM
(zzzzzH to FFEFFH)
12288 × 8 bit
(FCF00H to FFEFFH)
16384 × 8 bit
(FBF00H to FFEFFH)
20480 × 8 bit
(FAF00H to FFEFFH)
4 3
GRAM0 0
Control of invalid memory access detection
Detected lowest address for
read/instruction fetch
(execution) (yyyyyH)
20000H
30000H
40000H
2 1
GPORT GINT
0
GCSC
746