Renesas RL78 Series User Manual page 652

RL78/G1D
Figure 16-5. Format of Multiplication/Division Control Register (MDUC)
Address: F00E8H
Symbol <7>
MDUC DIVMODE
DIVMODE
0
0
0
0
1
1
MACOF
0
1
<Set condition>
• For the multiply-accumulator mode (unsigned)
The bit is set when the accumulated value goes outside the range from 00000000h to FFFFFFFFh.
• For the multiply-accumulator mode (signed)
The bit is set when the result of adding a positive product to a positive accumulated value exceeds
7FFFFFFFh and is negative, or when the result of adding a negative product to a negative accumulated
value exceeds 80000000h and is positive.
MACSF
0
1
Multiply-accumulator mode (unsigned):
Multiply-accumulator mode (signed):
Note 2
DIVST
0
1
Notes 1. Bits 1 and 2 are read-only bits.
2. The DIVST bit can only be set (1) in the division mode. In the division mode, division operation is started
by setting (1) the DIVST bit. The DIVST bit is automatically cleared (0) when the operation ends. In the
multiplication mode, operation is automatically started by setting the multiplier and multiplicand to
multiplication/division data register A (MDAH, MDAL), respectively.
Cautions 1. Do not rewrite the DIVMODE, MDSM bits during operation processing (while the DIVST bit is
1). If it is rewritten, the operation result will be an undefined value.
2. The DIVST bit cannot be cleared (0) by using software during division operation processing
(while the DIVST bit is 1).
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
CHAPTER 16 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR
Note 1
After reset: 00H R/W
<6> 5
MACMODE 0
MACMODE MDSM
0 0
0 1
1 0
1 1
0 0
1 0
Other than above
Overflow flag of multiply-accumulation result (accumulated value)
No overflow
With over flow
Sign flag of multiply-accumulation result (accumulated value)
The accumulated value is positive.
The accumulated value is negative.
Division operation processing complete
Starts division operation/division operation processing in progress
4 <3>
0 MDSM
Operation mode selection
Multiplication mode (unsigned) (default)
Multiplication mode (signed)
Multiply-accumulator mode (unsigned)
Multiply-accumulator mode (signed)
Division mode (unsigned), generation of a division completion
interrupt (INTMD)
Division mode (unsigned), not generation of a division completion
interrupt (INTMD)
Setting prohibited
The bit is always 0.
The bit indicates the sign bit of the accumulated value.
Division operation start/stop
<2> <1>
MACOF MACSF DIVST
<0>
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