Renesas RL78 Series User Manual page 578

RL78/G1D
14.5.14 Communication reservation
(1) When communication reservation function is enabled (bit n (IICRSVn) of IICA flag register n (IICFn) = 0)
To start master device communications when not currently using a bus, a communication reservation can be made to
enable transmission of a start condition when the bus is released. There are two modes under which the bus is not
used.
• When arbitration results in neither master nor slave operation
• When an extension code is received and slave operation is disabled (ACK is not returned and the bus was
released by setting bit 6 (LRELn) of IICA control register n0 (IICCTLn0) to 1 and saving communication).
If bit 1 (STTn) of the IICCTLn0 register is set to 1 while the bus is not used (after a stop condition is detected), a start
condition is automatically generated and wait state is set.
If an address is written to the IICA shift register n (IICAn) after bit 4 (SPIEn) of the IICCTLn0 register was set to 1, and
it was detected by generation of an interrupt request signal (INTIICAn) that the bus was released (detection of the stop
condition), then the device automatically starts communication as the master. Data written to the IICAn register before
the stop condition is detected is invalid.
When the STTn bit has been set to 1, the operation mode (as start condition or as communication reservation) is
determined according to the bus status.
● If the bus has been released .................................... a start condition is generated
● If the bus has not been released (standby mode) .... communication reservation
Check whether the communication reservation operates or not by using the MSTSn bit (bit 7 of the IICA status register
n (IICSn)) after the STTn bit is set to 1 and the wait time elapses.
Use software to secure the wait time calculated by the following expression.
Wait time from setting STTn = 1 to checking the MSTSn flag:
(IICWLn setting value + IICWHn setting value + 4)/f
Remarks 1. IICWLn: IICA low-level width setting register n
IICWHn: IICA high-level width setting register n
t : SDAAn and SCLAn signal falling times
F
f
MCK
2. n = 0
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
: IICA operation clock frequency
CHAPTER 14 SERIAL INTERFACE IICA
+ t 2
×
F
MCK
557