Renesas RL78 Series User Manual page 530

RL78/G1D
(2) Processing flow
SSmn
"L"
SEmn
"H"
SOEmn
"H"
SDRmn
SCLr output
SDAr output
SDAr input
Shift
register mn
INTIICr
TSFmn
transmission completed
Starting data transmission
No
Data transfer completed?
Stop condition generation
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 13-102. Timing Chart of Data Transmission
D7
D7
Figure 13-103. Flowchart of Simplified I
Address field
Writing data to SIOr
(SDRmn[7:0])
Transfer end interrupt
generated?
Yes
Responded ACK?
Yes
Yes
Data transmission
completed
CHAPTER 13 SERIAL ARRAY UNIT
Transmit data 1
D6 D5 D4 D3
D6 D5 D4 D3
Shift operation
2
C Data Transmission
Transmission start by writing
Wait for transmission complete.
No
(Clear the interrupt request flag)
ACK acknowledgment from the slave
If ACK (PEF = 0), to the next process
No
if NACK (PEF = 1), to error handling
Communication error
processing
D2 D1 D0
D2 D1 D0 ACK
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