Renesas RL78 Series User Manual page 254

RL78/G1D
Figure 7-58. Example of Set Contents of Registers to Measure Input Signal High-/Low-Level Width
(a) Timer mode register mn (TMRmn)
15 14
TMRmn
CKSmn1 CKSmn0
1/0 0
Operation clock (f
00B: Selects CKm0 as operation clock of channel n.
10B: Selects CKm1 as operation clock of channel n.
01B: Selects CKm2 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3).
11B: Selects CKm3 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3).
(b) Timer output register 0 (TO0)
Bit n
TO0
TO0n
0
(c) Timer output enable register 0 (TOE0)
Bit n
TOE0
TOE0n
0
(d) Timer output level register 0 (TOL0)
Bit n
TOL0
TOL0n
0
(e) Timer output mode register 0 (TOM0)
Bit n
TOM0
TOM0n
0
Note TMRm2, TMRm4, TMRm6:
TMRm1, TMRm3:
TMRm0, TMRm5, TMRm7:
Remark m: Unit number (m = 0), n: Channel number (n = 0 to 7)
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
13 12 11 10
Note
CCSmn STSmn2 STSmn1
M/S
0 0 0 0
Setting of MASTERmn bit (channels 2, 4, 6)
0: Independent channel operation function.
Setting of SPLITmn bit (channels 1, 3)
1: 16-bit timer mode.
Count clock selection
0: Selects operation clock (f
) selection
MCK
0: Outputs 0 from TO0n.
0: Stops the TO0n output operation by counting operation.
0: Cleared to 0 when TOM0n = 0 (master channel output mode).
0: Sets master channel output mode.
MASTERmn bit
SPLITmn bit
Fixed to 0
9 8 7 6 5
STSmn0 CISmn1 CISmn0
1 0 1 1/0 0
Operation mode of channel n
110B: Capture & one-count
Selection of TImn pin input edge
10B: Both edges (to measure low-level width)
11B: Both edges (to measure high-level width)
Start trigger selection
010B: Selects the TImn pin input valid edge.
).
MCK
CHAPTER 7 TIMER ARRAY UNIT
4 3 2 1
MDmn3 MDmn2 MDmn1
0 1 1 0
Setting of operation when counting is started
0: Does not generate INTTMmn when
counting is started.
0
MDmn0
0
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