Renesas RL78 Series User Manual page 563

RL78/G1D
Cautions1.
2. Note the minimum f
f
Fast mode: f
Fast mode plus: f
Normal mode: f
Remarks 1. Calculate the rise time (t
they differ depending on the pull-up resistance and wire load.
2. IICWLn: IICA low-level width setting register n
IICWHn: IICA high-level width setting register n
t : SDAAn and SCLAn signal falling times
F
t : SDAAn and SCLAn signal rising times
R
f
MCK
3. n = 0
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
The fastest operation frequency of the IICA operation clock (f
0 (PRSn) of the IICA control register n1 (IICCTLn1) to "1" only when the f
MHz.
operation frequency when setting the transfer clock. The minimum
CLK
operation frequency for serial interface IICA is determined according to the mode.
CLK
= 3.5 MHz (min.)
CLK
= 10 MHz (min.)
CLK
= 1 MHz (min.)
CLK
) and fall time (t
R
: IICA operation clock frequency
CHAPTER 14 SERIAL INTERFACE IICA
) of the SDAAn and SCLAn signals separately, because
F
) is 20 MHz (max.). Set bit
MCK
exceeds 20
CLK
542