Renesas RL78 Series User Manual page 183

RL78/G1D
f
CLK
Peripheral enable
register 0
(PER0)
Timer input select
register 0 (TIS0)
TIS2 TIS1 TIS0
f
SUB
f
IL
TI05
Remark f : Subsystem clock frequency
SUB
f : Low-speed on-chip oscillator clock frequency
IL
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 7-1. Entire Configuration of Timer Array Unit 0
Timer clock select register 0 (TPS0)
PRS031 PRS030 PRS021 PRS020
2
8
f /2 , f
CLK CLK
12
f /2 , f
CLK CLK
TAU0EN
Selector
TI00
Channel 0
Channel 1
TI01
TI02
Channel 2
Channel 3
TI03
TI04 Channel 4
Channel 5
TI06
Channel 6
TI07
Channel 7
PRS013 PRS012 PRS011 PRS010
2 4
Prescaler
1 2
f /2 , f /2 ,
CLK CLK
f
4 6
10 CLK
/2 , f /2 , f /2 ,
CLK CLK
14
/2 ,
Selector Selector
CK03 CK02 CK01
CHAPTER 7 TIMER ARRAY UNIT
PRS003 PRS002 PRS001 PRS000
4
0 15
/2 to f /2
CLK
Selector
CK00
INTTM00
(Timer interrupt)
TO01
INTTM01
INTTM01H
INTTM02
INTTM03
INTTM03H
INTTM04
TO05
INTTM05
TO06
INTTM06
TO07
INTTM07
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