Renesas RL78 Series User Manual page 215

RL78/G1D
(2) When valid edge of input signal via the TImn pin is selected (CCSmn = 1)
The count clock (f
TCLK
next rising f . The count clock (f
MCK
(when a noise filter is used, the delay becomes 3 to 4 clock).
Counting of timer count register mn (TCRmn) delayed by one period of f
because of synchronization with f
pin", as a matter of convenience.
Figure 7-23. Timing of f
f
MCK
TSmn (write)
TEmn
TImn input
Sampling wave
Rising edge
detection signal (f )
TCLK
<1> Setting TSmn bit to 1 enables the timer to be started and to become wait state for valid edge of input
signal via the TImn pin.
<2> The rise of input signal via the TImn pin is sampled by f
<3> The edge is detected by the rising of the sampled signal and the detection signal (count clock) is output.
Remarks 1.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
) becomes the signal that detects valid edge of input signal via the TImn pin and synchronizes
) is delayed for 1 to 2 period of f
TCLK
. But, this is described as "counting at valid edge of input signal via the TImn
CLK
and count clock (f
CLK
<1>
<2>
Edge detection
: Rising edge of the count clock
: Synchronization, increment/decrement of counter
2. f : CPU/peripheral hardware clock
CLK
f : Operation clock of channel n
MCK
3. The waveform of the input signal via TImn pin of the input pulse interval measurement, the
measurement of high/low width of input signal, and the delay counter, the one-shot pulse
output are the same.
CHAPTER 7 TIMER ARRAY UNIT
MCK
CLK
) (When CCSmn = 1, noise filter unused)
TCLK
<3>
.
MCK
from the input signal via the TImn pin
from rising edge of the count clock,
Edge detection
194