Renesas RL78 Series User Manual page 237

RL78/G1D
Figure 7-43. Operation Procedure of Interval Timer/Square Wave Output Function (1/2)
TAU
default
setting
Sets the TAUmEN bit of peripheral enable register 0
(PER0) to 1.
Sets timer clock select register m (TPSm).
Determines clock frequencies of CKm0 to CKm3.
Channel Sets timer mode register mn (TMRmn) (determines
default operation mode of channel).
setting Sets interval (period) value to timer data register mn
(TDRmn).
To use the TO0n output
Clears the TOM0n bit of timer output mode register 0
(TOM0) to 0 (master channel output mode).
Clears the TOL0n bit to 0.
Sets the TO0n bit and determines default level of the
TO0n output.
Sets the TOE0n bit to 1 and enables operation of TO0n.
Clears the port register and port mode register to 0.
Operation (Sets the TOE0n bit to 1 only if using TO0n output and
start resuming operation.).
Sets the TSmn (TSHm1, TSHm3) bit to 1.
The TSmn (TSHm1, TSHm3) bit automatically returns
to 0 because it is a trigger bit.
During Set values of the TMRmn register, TOM0n, and TOL0n
operation bits cannot be changed.
Set value of the TDRmn register can be changed.
The TCRmn register can always be read.
The TSRmn register is not used.
Set values of the TO0 and TOE0 registers can be
changed.
The TTmn (TTHm1, TTHm3) bit is set to 1.
Operation
The TTmn (TTHm1, TTHm3) bit automatically returns
stop
to 0 because it is a trigger bit.
The TOE0n bit is cleared to 0 and value is set to the TO0n bit.
(Remark is listed on the next page.)
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Software Operation
CHAPTER 7 TIMER ARRAY UNIT
Hardware Status
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Channel stops operating.
(Clock is supplied and some power is consumed.)
The TO0n pin goes into Hi-Z output state.
The TO0n default setting level is output when the port mode
register is in the output mode and the port register is 0.
TO0n does not change because channel stops operating.
The TO0n pin outputs the TO0n set level.
TEmn (TEHm1, TEHm3) = 1, and count operation starts.
Value of the TDRmn register is loaded to timer count
register mn (TCRmn). INTTMmn is generated and TO0n
performs toggle operation if the MDmn0 bit of the TMRmn
register is 1.
Counter (TCRmn) counts down. When count value reaches
0000H, the value of the TDRmn register is loaded to the
TCRmn register again and the count operation is continued.
By detecting TCRmn = 0000H, INTTMmn is generated and
TO0n performs toggle operation.
After that, the above operation is repeated.
TEmn (TEHm1, TEHm3), and count operation stops.
The TCRmn register holds count value and stops.
The TOmn output is not initialized but holds current status.
The TO0n pin outputs the TO0n bit set level.
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