Renesas RL78 Series User Manual page 560

RL78/G1D
14.3.8 Port mode register 6 (PM6)
This register sets the input/output of port 6 in 1-bit units.
When using the P60/SCLA0 pin as clock I/O and the P61/SDAA0 pin as serial data I/O, clear PM60 and PM61, and the
output latches of P60 and P61 to 0.
Set the IICEn bit (bit 7 of IICA control register n0 (IICCTLn0)) to 1 before setting the output mode because the
P60/SCLA0 and P61/SDAA0 pins output a low level (fixed) when the IICEn bit is 0.
The PM6 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Address: FFF26H
Symbol 7
PM6 1
PM6n
0
1
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 14-12. Format of Port Mode Register 6 (PM6)
After reset: FFH R/W
6 5
1 1
P6n pin I/O mode selection (n = 0 to 3)
Output mode (output buffer on)
Input mode (output buffer off)
CHAPTER 14 SERIAL INTERFACE IICA
4 3 2
1 PM63 PM62
1 0
PM61 PM60
539