Renesas RL78 Series User Manual page 694

RL78/G1D
18.3.2 Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H, MK3L)
The interrupt mask flags are used to enable/disable the corresponding maskable interrupt.
The MK0L, MK0H, MK1L, MK1H, MK2L, MK2H, and MK3L registers can be set by a 1-bit or 8-bit memory manipulation
instruction. When the MK0L and MK0H registers, the MK1L and MK1H registers, and the MK2L and MK2H registers are
combined to form 16-bit registers MK0, MK1, and MK2, they can be set by a 16-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
Remark If an instruction that writes data to this register is executed, the number of instruction execution clocks
increases by 2 clocks.
Figure 18-3. Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H, MK3L) (1/2)
Address: FFFE4H
Symbol <7>
MK0L PMK5
Address: FFFE5H
Symbol <7>
SREMK0
MK0H
TMMK01H
Address: FFFE6H
Symbol <7>
MK1L TMMK03
Address: FFFE7H
Symbol <7>
MK1H TMMK04
Address: FFFD4H
Symbol 7
MK2L 1
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
After reset: FFH R/W
6 <5>
1 PMK3
After reset: FFH R/W
<6> <5>
SRMK0 STMK0
CSIMK00
IICMK00
After reset: FFH R/W
<6> <5>
TMMK02 TMMK01
After reset: FFH R/W
6 5
1 1
After reset: FFH R/W
6 5
1 1
CHAPTER 18 INTERRUPT FUNCTIONS
4 3
1 1
<4> <3>
DMAMK1 DMAMK0
<4> <3>
TMMK00 IICAMK0 SREMK1
TMMK03H
4 3
1 1
4 <3>
1 PMK6 TMMK07
<2> <1> <0>
PMK0 LVIMK WDTIMK
2 <1> <0>
CSIMK21 CSIMK20
1
IICMK20
<2> <1> <0>
SRMK1 STMK1
<2> <1> <0>
ITMK RTCMK ADMK
<2> <1> <0>
TMMK06 TMMK05
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