Renesas RL78 Series User Manual page 680

RL78/G1D
● Procedure for forcibly terminating the DMA
transfer for one channel if both channels are used
Caution In example 3, the system is not required to wait two clock cycles after the DWAITn bit
Remarks 1. n: DMA channel number (n = 0, 1)
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 17-11. Forced Termination of DMA Transfer (2/2)
Example 3
DWAIT0 = 1
DWAIT1 = 1
DSTn = 0
DWAIT0 = 0
DWAIT1 = 0
DENn = 0
is set to 1. In addition, the system does not have to wait two clock cycles after clearing
the DSTn bit to 0, because more than two clock cycles elapse from when the DSTn bit
is cleared to 0 to when the DENn bit is cleared to 0.
2. 1 clock: 1/f (f : CPU clock)
CLK CLK
CHAPTER 17 DMA CONTROLLER
● Procedure for forcibly terminating the DMA
transfer for both channels if both channels are used
DWAIT0 = 1
DWAIT1 = 1
DST0 = 0
DST1 = 0
DWAIT0 = 0
DWAIT1 = 0
DEN0 = 0
DEN1 = 0
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