Renesas RL78 Series User Manual page 510

16-bit single-chip microcontrollers
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RL78/G1D
Figure 13-91. Flowchart of SNOOZE Mode Operation (EOCm1 = 0, SSECm = 0/1 or EOCm1 = 1, SSECm = 0)
INTSREq
Reading receive data from
the SDRmn[7:0] bits (RXDq
register) (8 bits) or the
SDRmn[8:0] bits (9 bits)
Writing 1 to the STm1 bit
Clear the SWCm bit to 0
Error processing
Change to the UART
reception baud rate in
normal operation
Writing 1 to the SSmn bit
Normal operation
Remarks 1. <1> to <12> in the figure correspond to <1> to <12> in Figure 13-89 Timing Chart of SNOOZE
Mode Operation (EOCm1 = 0, SSECm = 0/1) and Figure 13-90 Timing Chart of SNOOZE Mode
Operation (EOCm1 = 1, SSECm = 0).
2. m = 0; n = 1; q = 0
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Setting start
Does TSFmn = 0 on all
channels?
Yes
Writing 1 to the STmn bit
<1>
→ SEmn = 0
SAU default setting
Setting SSCm register
<2>
(SWCm = 1)
Writing 1 to the SSmn bit
<3>
→ SEm1 = 1
Enable interrupt
<4>
Entered the STOP mode
<5>
<6>
<7>
<8>
INTSRq
Reading receive data from
<9>
the SDRmn[7:0] bits (RXDq
register) (8 bits) or the
SDRmn[8:0] bits (9 bits)
<10>
Writing 1 to the STm1 bit
<11>
Clear the SWCm bit to 0
Change to the UART
reception baud rate in
normal operation
<12>
Writing 1 to the SSmn bit
Normal operation
CHAPTER 13 SERIAL ARRAY UNIT
No
The operation of all channels is also stopped to switch to the
STOP mode.
Channel 1 is specified for UART reception.
Change to the UART reception baud rate in SNOOZE mode
(SPSm register and bits 15 to 9 in SDRm1 register).
SNOOZE mode setting
Communication wait status
Clear interrupt request flag (XXIF), reset interrupt mask (XXMK)
and set interrupt enable (IE).
f
supplied to the SAU is stopped.
CLK
RxDq valid edge detected
(Entered the SNOOZE mode)
Input of the start bit on
the RxDq pin detected
(UART receive operation)
Transfer end interrupt (INTSRq) or
error interrupt (INTSREq) generated
The mode switches from SNOOZE to normal
operation.
To operation stop status (SEm1 = 0)
Reset SNOOZE mode setting.
Set the SPSm register and bits 15 to 9 in the
SDRm1 register.
To communication wait status (SEmn = 1)
489

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