Renesas RL78 Series User Manual page 641

16-bit single-chip microcontrollers
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RL78/G1D
15.4.4 Mode transition time
Table 15-2 shows the mode transition time.
Mode Transition
Exit from
Power off
POWER_DOWN
POWER_DOWN
RESET_RF
RESET_RF
POWER_DOWN
RESET_RF
STANDBY_RF
STANDBY_RF
RESET_RF
STANDBY_RF
POWER_DOWN
STANDBY_RF
IDLE_RF
IDLE_RF
STANDBY_RF
IDLE_RF
POWER_DOWN
IDLE_RF
SLEEP_RF
SLEEP_RF
IDLE_RF
IDLE_RF
DEEP_SLEEP
DEEP_SLEEP
IDLE_RF
IDLE_RF
SETUP_RF
SETUP_RF
RF transmission
SETUP_RF
RF reception
RF transmission
IDLE_RF
RF reception
IDLE_RF
SETUP_RF
POWER_DOWN
RF transmission
POWER_DOWN
RF reception
POWER_DOWN
Note
For the low width and high width, refer to the AC characteristics.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Table 15-2. Mode Transition Time
Entry to
The signal on the RFCTLEN pin being at the low level for two cycles of the RF slow clock
after the power-supply voltage has 1.6 V from 0 V
Two cycles of the RF slow clock following a transition of the signal on the RFCTLEN pin
from the low to the high level
Two cycles of the RF slow clock following a transition of the signal on the RFCTLEN pin
from the high to the low level
Two cycles of the RF slow clock following a transition of the signal on the CE_RF pin from
the low to the high level
After entering STANDBY_RF mode, this mode must be retained for at least the oscillation
stabilization time [550 µs + α (where α differs with the oscillator)].
Two cycles of the RF slow clock following a transition of the signal on the CE_RF pin from
the high to the low level
Two cycles of the RF slow clock following a transition of the signal on the RFCTLEN pin
from the high to the low level
(4 x 1/RF slow clock + 1/RF base clock x 6) following a transition of the signal on the
RESET_RF internal pin from the low to the high level
Low width (min.)
After entering STANDBY_RF mode, this mode must be retained for at least the oscillation
stabilization time [550 µs + α (where α differs with the oscillator)].
Two cycles of the RF slow clock following a transition of the signal on the RFCTLEN pin
from the high to the low level
Within a period of one cycle of the RF slow clock + (1 µs)
Within a period of one cycle of the RF base clock following a generation of the interrupt
Within a period of one cycle of the RF slow clock + (1 µs)
Within a period of one cycle of the RF base clock following a generation of the interrupt
1 µs
After entering SETUP_RF mode, the duration period is 11 µs.
150 µs
After entering RF transmission mode, the duration period is max. 376 µs and min. 80 µs.
150 µs
After entering RF reception mode, the duration period is min. 80 µs.
3 µs
1 µs
Two cycles of the RF slow clock following a transition of the signal on the RFCTLEN pin
from the high to the low level
Two cycles of the RF slow clock following a transition of the signal on the RFCTLEN pin
from the high to the low level
Two cycles of the RF slow clock following a transition of the signal on the RFCTLEN pin
from the high to the low level
Transition Time
Note
of the RESET_RF internal pin.
CHAPTER 15 RF TRANSCEIVER
620

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