Renesas RL78 Series User Manual page 590

16-bit single-chip microcontrollers

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An example of the processing procedure of the slave with the INTIICAn interrupt is explained below (processing is

performed assuming that no extension code is used). The INTIICAn interrupt checks the status, and the following

operations are performed.

<1> Communication is stopped if the stop condition is issued.

<2> If the start condition is issued, the address is checked and communication is completed if the address does not

match. If the address matches, the communication mode is set, wait is cancelled, and processing returns from

the interrupt (the ready flag is cleared).

<3> For data transmit/receive, only the ready flag is set. Processing returns from the interrupt with the I

remaining in the wait state.

<1> to <3> above correspond to <1> to <3> in Figure 14-31 Slave Operation Flowchart (2).

INTIICAn generated

Set ready flag

Interrupt servicing completed

14.5.17 Timing of I

C interrupt request (INTIICAn) occurrence

The timing of transmitting or receiving data and generation of interrupt request signal INTIICAn, and the value of the

IICA status register n (IICSn) when the INTIICAn signal is generated are shown below.

ST: Start condition

AD6 to AD0: Address

R/W: Transfer direction specification

ACK: Acknowledge

D7 to D0: Data

SP: Stop condition

R01UH0515EJ0120 Rev.1.20

Dec 16, 2016

Figure 14-31. Slave Operation Flowchart (2)

Communication direction flag

Set communication mode flag

CHAPTER 14 SERIAL INTERFACE IICA

Clear ready flag

Clear communication direction

flag, ready flag, and

communication mode flag

Rl78/g1d R5f11agg R5f11agh R5f11agj