Renesas RL78 Series User Manual page 658

RL78/G1D
Figure 16-9. Timing Diagram of Multiply-Accumulation (signed) Operation
(2 × 3 + (–4) = 2
Operation clock
<1>
MDUC
00H 48H
MDSM L
MDCH 0000H
MDCL 0000H
MDAL 0000H
MDAH 0000H
MDBH 0000H
MDBL 0000H
INTMD
MACOF
MACSF
L
<2>
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
CHAPTER 16 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR
→
32767 × (–1) + (–2147483647) = –2147450882 (overflow occurs.))
4AH
<3>
FFFFH
FFFCH
0002H
0003H
<3>
<4> <5> <6> <7> <8>
<9> <3>
0000H 8000H
0002H
<10>, <11>
0000H
0006H
<9>
<3>
<2> <4> <5> <6>
4CH
0001H
7FFFH
FFFFH
<12>
<7> <8>
7FFFH
8002H
0000H
0001H
637