Renesas RL78 Series User Manual page 430

RL78/G1D
(4) Processing flow (in continuous transmission mode)
Figure 13-30. Timing Chart of Master Transmission (in Continuous Transmission Mode)
<1>
SSmn
STmn
SEmn
SDRmn
SCKp pin
SOp pin
Shift
register mn
INTCSIp
MDmn0
TSFmn
BFFmn
<2>
(Note)
Note If transmit data is written to the SDRmn register while the BFFmn bit of serial status register mn (SSRmn) is
1 (valid data is stored in serial data register mn (SDRmn)), the transmit data is overwritten.
Caution The MDmn0 bit of serial mode register mn (SMRmn) can be rewritten even during operation.
However, rewrite it before transfer of the last bit is started, so that it will be rewritten before the
transfer end interrupt of the last transmit data.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 for m = 0, n = 0, 1 for m = 1),
p: CSI number (p = 00, 20, 21), mn = 00, 10, 11
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
(Type 1: DAPmn = 0, CKPmn = 0)
Transmit data 1 Transmit data 2
Transmit data 1
Shift operation
Data transmission
<3> <2>
CHAPTER 13 SERIAL ARRAY UNIT
Transmit data 2
Shift operation
Data transmission
<3> <2>
Transmit data 3
Transmit data 3
Shift operation
Data transmission
<4>
<3>
<6>
<5>
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