Renesas RL78 Series User Manual page 673

RL78/G1D
Figure 17-7. Example of Setting for CSI Consecutive Transmission
DRA0 = FB00H
DBC0 = 0100H
Setting for CSI transfer
Note The DST0 flag is automatically cleared to 0 when a DMA transfer is completed.
Writing the DEN0 flag is enabled only when DST0 = 0. To terminate a DMA transfer without waiting for
occurrence of the interrupt of DMA0 (INTDMA0), set the DST0 bit to 0 and then the DEN0 bit to 0 (for
details, refer to 17.5.5 Forced termination by software).
The fist trigger for consecutive transmission is not started by the interrupt of CSI. In this example, it is started by a
software trigger.
CSI transmission of the second time and onward is automatically executed.
A DMA interrupt (INTDMA0) occurs when the last transmit data has been written to the data register.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Start
DEN0 = 1
DSA0 = 48H
DMC0 = 48H
DST0 = 1
DMA is started.
STG0 = 1
INTCSI20 occurs.
User program
processing
Occurrence of
INTDMA0
DST0 = 0
DEN0 = 0
RETI
End
DMA0 transfer
CSI
transmission
Note
CHAPTER 17 DMA CONTROLLER
Hardware operation
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