Renesas RL78 Series User Manual page 164

RL78/G1D
Table 6-3. CPU Clock Transition and SFR Register Setting Examples (2/5)
(4) CPU clock changing from high-speed on-chip oscillator clock (B) to high-speed system clock (C)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(B) → (C)
(X1 clock: 1 MHz ≤ f ≤ 10 MHz)
X
(B) → (C)
(X1 clock: 10 MHz < f ≤ 20 MHz)
X
(B) → (C)
(external main clock)
Notes 1. The clock operation mode control register (CMC) can be written only once by an 8-bit memory
manipulation instruction after reset release. This setting is not necessary if it has already been set.
2. Set the oscillation stabilization time as follows.
● Desired the oscillation stabilization time counter status register (OSTC) oscillation stabilization time
Oscillation stabilization time set by the oscillation stabilization time select register (OSTS)
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
CHAPTER 30 ELECTRICAL SPECIFICATIONS).
(5) CPU clock changing from high-speed on-chip oscillator clock (B) to subsystem clock (D)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(B) → (D)
(XT1 clock)
(B) → (D)
(external sub clock)
Note The clock operation mode control register (CMC) can be written only once by an 8-bit memory manipulation
instruction after reset release. This setting is not necessary if it has already been set.
Remarks 1. ×: don't care
2. (A) to (J) in Table 6-3 correspond to (A) to (J) in Figure 6-16.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Note 1
CMC Register
EXCLK OSCSEL AMPH
0 1
0 1
1 1
Unnecessary if these registers
are already set
CMC Register
EXCLKS OSCSELS
0 1 00: Low power
consumption oscillation
01: Normal oscillation
10: Ultra-low power
consumption oscillation
1 1
Unnecessary if these registers
are already set
CHAPTER 6 CLOCK GENERATOR
OSTS CSC
Register Register
MSTOP
0 Note 2 0
1 Note 2 0
× Note 2 0 Must not be checked
Unnecessary if the CPU is operating with
the high-speed system clock
Note
CSC
Register
AMPHS1,0 XTSTOP
0
× 0
Unnecessary if the CPU
is operating with the
subsystem clock
OSTC Register CKC
Register
MCM0
Must be checked 1
Must be checked 1
1
Waiting for CKC
Oscillation Register
Stabilization
CSS
Necessary 1
Necessary 1
≤
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