Renesas RL78 Series User Manual page 700

RL78/G1D
18.3.5 Program status word (PSW)
The program status word is a register used to hold the instruction execution result and the current status for an interrupt
request. The IE flag that sets maskable interrupt enable/disable and the ISP0 and ISP1 flags that controls multiple
interrupt servicing are mapped to the PSW.
Besides 8-bit read/write, this register can carry out operations using bit manipulation instructions and dedicated
instructions (EI and DI). When a vectored interrupt request is acknowledged, if the BRK instruction is executed, the
contents of the PSW are automatically saved into a stack and the IE flag is reset to 0. Upon acknowledgment of a
maskable interrupt request, if the value of the priority specification flag register of the acknowledged interrupt is not 00, its
value minus 1 is transferred to the ISP0 and ISP1 flags. The PSW contents are also saved into the stack with the PUSH
PSW instruction. They are restored from the stack with the RETI, RETB, and POP PSW instructions.
Reset signal generation sets PSW to 06H.
<7> <6> <5>
PSW IE Z RBS1
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 18-6. Configuration of Program Status Word
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AC RBS0 ISP1 ISP0
CHAPTER 18 INTERRUPT FUNCTIONS
0 After reset
CY 06H
Used when normal instruction is executed
ISP1 ISP0 Priority of interrupt currently being serviced
0 Enables interrupt of level 0
0
(while interrupt of level 1 or 0 is being serviced).
1 Enables interrupt of level 0 and 1
0
(while interrupt of level 2 is being serviced).
1 0 Enables interrupt of level 0 to 2
(while interrupt of level 3 is being serviced).
1 1 Enables all interrupts
(waits for acknowledgment of an interrupt).
Interrupt request acknowledgment enable/disable
IE
0 Disabled
1 Enabled
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