Renesas RL78 Series User Manual page 715

RL78/G1D
Reset signal
Status of CPU
Subsystem clock
(XT1 oscillation)
Note For the reset processing time, see CHAPTER 20 RESET FUNCTION.
For the reset processing time of the power-on-reset circuit (POR) and voltage detector (LVD), see
CHAPTER 21 POWER-ON-RESET CIRCUIT.
19.3.2 STOP mode
(1) STOP mode setting and operating statuses
The STOP mode is set by executing the STOP instruction, and it can be set only when the CPU clock before the
setting was the high-speed on-chip oscillator clock, X1 clock, or external main system clock.
Caution Because the interrupt request signal is used to clear the STOP mode, if the interrupt mask flag is 0
(the interrupt processing is enabled) and the interrupt request flag is 1 (the interrupt request signal
is generated), the STOP mode is immediately cleared if set when the STOP instruction is executed
in such a situation. Accordingly, once the STOP instruction is executed, the system returns to its
normal operating mode after the elapse of release time from the STOP mode.
The operating statuses in the STOP mode are shown below.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 19-2. HALT Mode Release by Reset (2/2)
(c) When subsystem clock is used as CPU clock
HALT
instruction
Normal operation
(subsystem clock)
HALT mode
Oscillates
CHAPTER 19 STANDBY FUNCTION
Normal operation mode
Reset
(high-speed on-chip
Note
period
oscillator clock)
Oscillation Oscillation
stopped
stopped
Oscillates
Oscillation stabilization time
(check by using OSTC register)
Starting XT1 oscillation is
specified by software.
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