Renesas RL78 Series User Manual page 736

RL78/G1D
Figure 21-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit
(c) LVD reset mode (option byte 000C1H: LVIMDS1 = 1, LVIMDS0 = 1)
Supply voltage (V
Lower limit voltage for guaranteed operation
V = 1.51 V ( TYP.)
POR
V = 1.50 V ( TYP.)
PDR
High-speed on-chip
oscillator clock (f
system clock (f
(when X1 oscillation
CPU Operation stops
Internal reset signal
Notes 1. The internal reset processing time includes the oscillation accuracy stabilization time of the high-speed on-
chip oscillator clock.
2. The high-speed on-chip oscillator clock and a high-speed system clock or subsystem clock can be selected
as the CPU clock. To use the X1 clock, use the oscillation stabilization time counter status register (OSTC)
to confirm the lapse of the oscillation stabilization time. To use the XT1 clock, use the timer function for
confirmation of the lapse of the stabilization time.
3. The time until normal operation starts includes the following LVD reset processing time after the LVD
detection level (V
the V (1.51 V, typ.) is reached.
POR
LVD reset processing time: 0 ms to 0.0701 ms (max.)
4. When the power supply voltage is below the lower limit for operation and the power supply voltage is then
restored after an internal reset is generated only by the voltage detector (LVD), the following LVD reset
processing time is required after the LVD detection level (V
LVD reset processing time: 0.0511 ms (typ.), 0.0701 ms (max.)
Remarks 1. V , V
LVDH
V : POR power supply rise detection voltage
POR
V : POR power supply fall detection voltage
PDR
2. When the LVD interrupt mode is selected (option byte 000C1H: LVIMD1 = 0, LVIMD0 = 1), the time until
normal operation starts after power is turned on is the same as the time specified in Note 3 of Figure 21-
2 (3).
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
and Voltage Detector (3/3)
)
DD
V
LVD
0 V
Wait for oscillation
accuracy stabilization
)
IH
High-speed
)
MX
is selected)
Voltage stabilization wait + POR reset
processing time 1.64 ms (TY P.),
3.10 ms (MAX.)
) is reached as well as the voltage stabilization wait + POR reset processing time after
LVD
: LVD detection voltage
LVDL
CHAPTER 21 POWER-ON-RESET CIRCUIT
Note 1
Starting oscillation
is specified by software
Normal operation
Reset period
(high-speed on-chip
(oscillation
oscillator clock) Note 2
stop)
LVD reset processing
Note 3
time
) is reached.
LVD
Wait for oscillation
Note 1
accuracy stabilization
Starting oscillation
is specified by software
Normal operation Reset period
(high-speed on-chip
(oscillation
oscillator clock) Note 2
stop)
LVD reset processing
Note 4
time
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